Packages that receive integrated circuit chips include a substrate that has input/output (I/O) pins on a surface. The I/O pins are attached to the substrate to form an array that is referred to as a Pin Grid Array (PGA). As chips and packages assume increased function, there is a need for a higher number of I/O pins. This increases both the density and the number of pins in the array, and requires populating the surface completely with pins.
The I/O pins should be uniformly electroplated to deposit a metal or alloy, e.g., gold, thereon to satisfy performance requirements. As illustrated in FIG. 1, electroplating is conventionally performed on a package 8 by taking a conductive plate 10, placing the conductive plate 10 in contact with pins 12 of the PGA 14 extending from a substrate 16 to short out the pins 12, placing the conductive plate 10 and pins 12 in an electroplating bath (not shown) containing an electroplating solution and applying a current to the conductive plate 10 to effect electroplating. As PGAs become more densely packed and fully populated, the solution cannot flow freely about all the pins 12 due to the presence of the conductive plate 10 resulting in the performance loss due to nonuniform electroplating. Undesirably, there is thicker plating deposition on the outer pin 18 and progressively thinner deposition on interior pins 20. This condition of non-uniform plating is further exacerbated by a decrease in the length of the pins and by any increase in the density of the array. Similar shortcomings will occur with other processes such as electroetching, leading to non-uniform etch rates.
A method of performing a process using electricity in the process on a feature such as a pin that overcomes some of the aforementioned shortcomings is highly desirable.